• Would you stake your reputation on an untested design?

    What would happen if your clients find out about the flaws in your IP before you do? Only methodically tested IP with a carefully designed assessment regime gives you assurances that your IP is solid.

    Traditional testing methods exposed
  • Advanced Design Verification paradigm

    Traditional DV is unwieldy and inadequate. Enter the modern age of design verification without the pricy entry ticket.

    Key advantages of our approach
  • Slash overhead costs

    Take advantage of sophisticated tools that support your design effort at minimal cost. Combine open source with our expertise to yield infrastructure that costs practically nothing.

    How much can you save?
  • Your DV partner

    We are more than a service provider. We are invested in your success, working hard to ensure an efficient and effective design verification system that suits your needs and corporate culture.

    Contact us now
How Design Verification Will Fast-Track Your Fabless FPGA Design Shop
All modern, well-funded, state-of-the-art fabless design companies achieve product integrity and a smooth workflow via sophisticated design verification tools. Automated systems remove the grunt work from logistics and debugging, freeing designers and DV engineers to focus on feature development instead of dev ops and “manual labor”.

If your fabless FPGA shop is still using ad hoc methods and primitive tools, then you pay the price in two major ways:

The first cost is time to market. The development timeline is punished heavily when manual and semi-manual ad hoc testing methods are used. Designers spend far more time on non-digital design work than developing features and the resulting IP is less robust
The second cost comes due at the time the IP is sold. Typical clients of smaller IP shops are large, modern, state of the art design companies that practice systematic design verification as part of their product development process. If they buy IP without robust design verification applied, they are taking a huge risk, lowering the value of the IP product. They will require DV “proof” to go with the purchased IP. Supplying state-of-the-art test benches and environments raises the value of your company’s product.
These companies trust Datum with DV
Find out first hand why our approach is changing FPGA projects forever

Key Advantages

Always Have a Working Version of the Design
Continuous Integration (CI) enables an organization to always have the latest working version of the design on hand and ready for sale even as new features are under development.
Know Which Features Work
As development advances, some features may be further developed than others. Automated testing highlights which features meet specifications, so you always know the status of your market-ready design.
Basics Always Work
There is nothing more annoying than a time-consuming bug that boils down to register implementation not matching specifications or UVM boiler-plate code malfunctions. DV tools handle these for you, so you will not get caught by basic problems again.
Know Exactly Where the Problems Are
Advanced DV debugging facilities help you identify problematic areas of the design and quickly triangulate to the root cause.
Software development can commence as soon as registers are accessible with read/write access via a functional control plane. Driver development is smoother and completes earlier based on a solid understanding of which design areas are operational as the project progresses.
Get the benefits
... and find out first hand why our clients choose Datum
Compare our approach
Minimal DV
Modern DV
Bugs are mostly discovered in the lab at 30 times the cost of in simulation.
Most bugs are found in simulation
It takes extensive time recreating the bugs in simulation
Bug conditions can be re-created at any time in simulation
Bug investigation involves expensive testers. Largely guesswork as design is mostly a black box
Debugging via transaction/scoreboard logs and waveform viewer
Primary tools: logic analysers*, protocol analyzers (lab)
Primary Tools: Simulator, DV Ops
Implementation, lab testing, manual bug recreation in simulation, and brute-force analysis
HDL simulation, constrained-random stimulus, regression-based hardening, minimal lab debugging required

Free consultation


Provide us with your design architecture block diagrams and we will recommend suitable Datum UVM code templates and libraries to get the job done. If you prefer to keep your design confidential, we can have a phone or zoom conversation to discuss your best way forward.

Test Modes

Test Mode
Minimal DV
Datum DV
SystemVerilog Simulator
$50,000 - $99,999 per seat per year
Free (Vivado)
Dev Ops
From scratch each project
Configurable and extensible platform
UVM Code Templates
From scratch each project
Extensible open-source
Overnight/weekend bug hunt/hardening
Regression reports
HTML & Jenkins
Support/use SVUnit/VUnit flow
Constrained-random stimulus
Instantaneous sanity check
Functional coverage
Continuous Integration
Compatible “out-of-the-box” with all simulators
If you're tired of these problems, it's time for a new approach
How Good DV shortens the Design Cycle
... and Saves you Money

If owners and managers were to track the time spent on feature development vs. operational friction at a fabless design shop without DV Ops and a modern DV approach, they would be horrified. We know they would find low productivity because we have observed homebrew approaches in the field. What seems like a simple task becomes an endless project, becoming a bottleneck to designers and sapping resources.

There is of course overhead in setting up a proper design verification system and a learning curve for designers. Does the effort justify the results?

According to our analysis, the advantages far outweigh the up-front costs when building upon hardened DV Ops tools and proven VIP libraries. After designers spend a week or so learning the ropes, much of the complexity disappears into the fabric of the development stack. This reduces operational friction by:

1 - Manual Labor
Ensuring that newly committed features don’t break working features without requiring “manual labor” from designers.
2 - Scripting
Reducing to near zero time spent developing/debugging automation.
3 - Boiler plate
Using documented and proven code for DV basics.
Keep Your Project On Track
Accelerate your design cycle with fully featured design verification you can afford. Contact us to find out how we can get you on track right now.
The expertise required to set up the design verification system is available at a fraction of the cost of even a single commercial simulator license.
... and the results speak for themselves
Advantages of Modern Design Verification

The biggest immediate advantage gained from DV Ops is continuous integration. This provides automatic, nearly instantaneous feedback on design changes as they are checked in. If features break, a full report is generated showing which tests failed and which changes broke the code. All stakeholders are alerted. If no problems are found, success is confirmation, and the design process advances.

By contrast, fabless design shops without continuous integration depend on engineers to “do the right thing” and run the correct set of tests by hand before committing their changes. The team must wait for regression reports run over-night and designers get the bad news the following morning.

The biggest overall advantage of design verification is accelerating the design cycle. Rather than loosing their train of thought with unnecessary interruptions, design engineers remain focused throughout the day, rather than suffering distractions while waiting for licenses or writing automation scripts. In the life cycle of the design, this results in much less operational friction and therefore faster time to market. Money comes to the business sooner to fund additional feature development, kicking off a virtuous circle of design excellence, a rich feature set and a well funded operation. In contrast, longer design cycles mean more outside investments required, with the associated loss of control and future profits.
Tap into our expertise

Modernize your DV

Modern DV eliminates laborious lab debugs, provides an excellent indication of where to locate bugs, and provides an up-to-date design status, module by module.
Modern DV ensures that there is always a working version of the design available. This includes all features that have passed extensive tests, even if further features are in development. Assuming version N+1 broke the codebase, version N is ready for sale with a robust set of features. This is possible because Datum provides you with a system based on a free simulator, allowing you to run sanity regressions constantly without draining the simulator seat licences required to develop new features.
Right now, modern design verification will set your company ahead of your peers. Soon, failure to implement modern design verification will put your company behind your competitors.
Why Hire Datum
With so many compelling benefits to design verification, why are so many small- and medium-sized fabless design shops without it? Our clients tell us the two key barriers are cost and insufficient expertise. Datum helps with both.

Once a design verification workstation is set up, it can be cloned at no cost. Each of your design engineers has access to a capable and free design simulator and this supports the extensive design verification system that we offer. It also eliminates queuing for a single seat commercial simulator license.

Automation is at the core of what we do, and it is a forgone conclusion that any design verification system that we configure comes with a high degree of automation customized to suit your unique design and environmental requirements.

Our services cost less than half the outlay of a single simulator licence for one year, not to mention the additional months added to the project timeline when proper design verification is not used. By hiring us to set up an open-source system, you are financially ahead.

Datum is the industry leader in combining the free Xilinx Vivado simulator with free and open-source libraries to produce an industrial design verification system that is as good as any industry solution.

To bring modern DV practices to your fabless shop, contact us:

Get a Quote


Take the first step towards full design verification now. Fill out the contact form below because we can start a conversation about your needs so that your project gains from a solid and affordable design verification platform.

Email: This email address is being protected from spambots. You need JavaScript enabled to view it.

Phone: +1 (647) 812-8340